/**
  **************************************************************************************
  * @file    REG_DMA.h
  * @brief   DMA Head File
  *
  * @version V0.01
  * @date    12/5/2018
  * @author  Eastsoft MCU Software Team
  * @note
  *
  * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
  *
  **************************************************************************************
  */

#ifndef __DMA_H__
#define __DMA_H__


/******************************************************************************/
/*                              设备特殊寄存器结构定义                        */
/******************************************************************************/

/*   允许匿名结构和匿名联合    */
/* #pragma anon_unions */

/****************** Bit definition for DMA_IER register ************************/

#define  DMA_IER_CH5TABIE_POS  11U 
#define  DMA_IER_CH5TABIE_MSK  BIT(DMA_IER_CH5TABIE_POS)

#define  DMA_IER_CH5BTDIE_POS  10U 
#define  DMA_IER_CH5BTDIE_MSK  BIT(DMA_IER_CH5BTDIE_POS)

#define  DMA_IER_CH4TABIE_POS  9U 
#define  DMA_IER_CH4TABIE_MSK  BIT(DMA_IER_CH4TABIE_POS)

#define  DMA_IER_CH4BTDIE_POS  8U 
#define  DMA_IER_CH4BTDIE_MSK  BIT(DMA_IER_CH4BTDIE_POS)

#define  DMA_IER_CH3TABIE_POS  7U 
#define  DMA_IER_CH3TABIE_MSK  BIT(DMA_IER_CH3TABIE_POS)

#define  DMA_IER_CH3BTDIE_POS  6U 
#define  DMA_IER_CH3BTDIE_MSK  BIT(DMA_IER_CH3BTDIE_POS)

#define  DMA_IER_CH2TABIE_POS  5U 
#define  DMA_IER_CH2TABIE_MSK  BIT(DMA_IER_CH2TABIE_POS)

#define  DMA_IER_CH2BTDIE_POS  4U 
#define  DMA_IER_CH2BTDIE_MSK  BIT(DMA_IER_CH2BTDIE_POS)

#define  DMA_IER_CH1TABIE_POS  3U 
#define  DMA_IER_CH1TABIE_MSK  BIT(DMA_IER_CH1TABIE_POS)

#define  DMA_IER_CH1BTDIE_POS  2U 
#define  DMA_IER_CH1BTDIE_MSK  BIT(DMA_IER_CH1BTDIE_POS)

#define  DMA_IER_CH0TABIE_POS  1U 
#define  DMA_IER_CH0TABIE_MSK  BIT(DMA_IER_CH0TABIE_POS)

#define  DMA_IER_CH0BTDIE_POS  0U 
#define  DMA_IER_CH0BTDIE_MSK  BIT(DMA_IER_CH0BTDIE_POS)

/****************** Bit definition for DMA_IDR register ************************/

#define  DMA_IDR_CH5TABID_POS  11U 
#define  DMA_IDR_CH5TABID_MSK  BIT(DMA_IDR_CH5TABID_POS)

#define  DMA_IDR_CH5BTDID_POS  10U 
#define  DMA_IDR_CH5BTDID_MSK  BIT(DMA_IDR_CH5BTDID_POS)

#define  DMA_IDR_CH4TABID_POS  9U 
#define  DMA_IDR_CH4TABID_MSK  BIT(DMA_IDR_CH4TABID_POS)

#define  DMA_IDR_CH4BTDID_POS  8U 
#define  DMA_IDR_CH4BTDID_MSK  BIT(DMA_IDR_CH4BTDID_POS)

#define  DMA_IDR_CH3TABID_POS  7U 
#define  DMA_IDR_CH3TABID_MSK  BIT(DMA_IDR_CH3TABID_POS)

#define  DMA_IDR_CH3BTDID_POS  6U 
#define  DMA_IDR_CH3BTDID_MSK  BIT(DMA_IDR_CH3BTDID_POS)

#define  DMA_IDR_CH2TABID_POS  5U 
#define  DMA_IDR_CH2TABID_MSK  BIT(DMA_IDR_CH2TABID_POS)

#define  DMA_IDR_CH2BTDID_POS  4U 
#define  DMA_IDR_CH2BTDID_MSK  BIT(DMA_IDR_CH2BTDID_POS)

#define  DMA_IDR_CH1TABID_POS  3U 
#define  DMA_IDR_CH1TABID_MSK  BIT(DMA_IDR_CH1TABID_POS)

#define  DMA_IDR_CH1BTDID_POS  2U 
#define  DMA_IDR_CH1BTDID_MSK  BIT(DMA_IDR_CH1BTDID_POS)

#define  DMA_IDR_CH0TABID_POS  1U 
#define  DMA_IDR_CH0TABID_MSK  BIT(DMA_IDR_CH0TABID_POS)

#define  DMA_IDR_CH0BTDID_POS  0U 
#define  DMA_IDR_CH0BTDID_MSK  BIT(DMA_IDR_CH0BTDID_POS)

/****************** Bit definition for DMA_IVS register ************************/

#define  DMA_IVS_CH5TABIVS_POS  11U 
#define  DMA_IVS_CH5TABIVS_MSK  BIT(DMA_IVS_CH5TABIVS_POS)

#define  DMA_IVS_CH5BTDIVS_POS  10U 
#define  DMA_IVS_CH5BTDIVS_MSK  BIT(DMA_IVS_CH5BTDIVS_POS)

#define  DMA_IVS_CH4TABIVS_POS  9U 
#define  DMA_IVS_CH4TABIVS_MSK  BIT(DMA_IVS_CH4TABIVS_POS)

#define  DMA_IVS_CH4BTDIVS_POS  8U 
#define  DMA_IVS_CH4BTDIVS_MSK  BIT(DMA_IVS_CH4BTDIVS_POS)

#define  DMA_IVS_CH3TABIVS_POS  7U 
#define  DMA_IVS_CH3TABIVS_MSK  BIT(DMA_IVS_CH3TABIVS_POS)

#define  DMA_IVS_CH3BTDIVS_POS  6U 
#define  DMA_IVS_CH3BTDIVS_MSK  BIT(DMA_IVS_CH3BTDIVS_POS)

#define  DMA_IVS_CH2TABIVS_POS  5U 
#define  DMA_IVS_CH2TABIVS_MSK  BIT(DMA_IVS_CH2TABIVS_POS)

#define  DMA_IVS_CH2BTDIVS_POS  4U 
#define  DMA_IVS_CH2BTDIVS_MSK  BIT(DMA_IVS_CH2BTDIVS_POS)

#define  DMA_IVS_CH1TABIVS_POS  3U 
#define  DMA_IVS_CH1TABIVS_MSK  BIT(DMA_IVS_CH1TABIVS_POS)

#define  DMA_IVS_CH1BTDIVS_POS  2U 
#define  DMA_IVS_CH1BTDIVS_MSK  BIT(DMA_IVS_CH1BTDIVS_POS)

#define  DMA_IVS_CH0TABIVS_POS  1U 
#define  DMA_IVS_CH0TABIVS_MSK  BIT(DMA_IVS_CH0TABIVS_POS)

#define  DMA_IVS_CH0BTDIVS_POS  0U 
#define  DMA_IVS_CH0BTDIVS_MSK  BIT(DMA_IVS_CH0BTDIVS_POS)

/****************** Bit definition for DMA_RIF register ************************/

#define  DMA_RIF_CH5TABRIF_POS  11U 
#define  DMA_RIF_CH5TABRIF_MSK  BIT(DMA_RIF_CH5TABRIF_POS)

#define  DMA_RIF_CH5BTDRIF_POS  10U 
#define  DMA_RIF_CH5BTDRIF_MSK  BIT(DMA_RIF_CH5BTDRIF_POS)

#define  DMA_RIF_CH4TABRIF_POS  9U 
#define  DMA_RIF_CH4TABRIF_MSK  BIT(DMA_RIF_CH4TABRIF_POS)

#define  DMA_RIF_CH4BTDRIF_POS  8U 
#define  DMA_RIF_CH4BTDRIF_MSK  BIT(DMA_RIF_CH4BTDRIF_POS)

#define  DMA_RIF_CH3TABRIF_POS  7U 
#define  DMA_RIF_CH3TABRIF_MSK  BIT(DMA_RIF_CH3TABRIF_POS)

#define  DMA_RIF_CH3BTDRIF_POS  6U 
#define  DMA_RIF_CH3BTDRIF_MSK  BIT(DMA_RIF_CH3BTDRIF_POS)

#define  DMA_RIF_CH2TABRIF_POS  5U 
#define  DMA_RIF_CH2TABRIF_MSK  BIT(DMA_RIF_CH2TABRIF_POS)

#define  DMA_RIF_CH2BTDRIF_POS  4U 
#define  DMA_RIF_CH2BTDRIF_MSK  BIT(DMA_RIF_CH2BTDRIF_POS)

#define  DMA_RIF_CH1TABRIF_POS  3U 
#define  DMA_RIF_CH1TABRIF_MSK  BIT(DMA_RIF_CH1TABRIF_POS)

#define  DMA_RIF_CH1BTDRIF_POS  2U 
#define  DMA_RIF_CH1BTDRIF_MSK  BIT(DMA_RIF_CH1BTDRIF_POS)

#define  DMA_RIF_CH0TABRIF_POS  1U 
#define  DMA_RIF_CH0TABRIF_MSK  BIT(DMA_RIF_CH0TABRIF_POS)

#define  DMA_RIF_CH0BTDRIF_POS  0U 
#define  DMA_RIF_CH0BTDRIF_MSK  BIT(DMA_RIF_CH0BTDRIF_POS)

/****************** Bit definition for DMA_IFM register ************************/

#define  DMA_IFM_CH5TABIFM_POS  11U 
#define  DMA_IFM_CH5TABIFM_MSK  BIT(DMA_IFM_CH5TABIFM_POS)

#define  DMA_IFM_CH5BTDIFM_POS  10U 
#define  DMA_IFM_CH5BTDIFM_MSK  BIT(DMA_IFM_CH5BTDIFM_POS)

#define  DMA_IFM_CH4TABIFM_POS  9U 
#define  DMA_IFM_CH4TABIFM_MSK  BIT(DMA_IFM_CH4TABIFM_POS)

#define  DMA_IFM_CH4BTDIFM_POS  8U 
#define  DMA_IFM_CH4BTDIFM_MSK  BIT(DMA_IFM_CH4BTDIFM_POS)

#define  DMA_IFM_CH3TABIFM_POS  7U 
#define  DMA_IFM_CH3TABIFM_MSK  BIT(DMA_IFM_CH3TABIFM_POS)

#define  DMA_IFM_CH3BTDIFM_POS  6U 
#define  DMA_IFM_CH3BTDIFM_MSK  BIT(DMA_IFM_CH3BTDIFM_POS)

#define  DMA_IFM_CH2TABIFM_POS  5U 
#define  DMA_IFM_CH2TABIFM_MSK  BIT(DMA_IFM_CH2TABIFM_POS)

#define  DMA_IFM_CH2BTDIFM_POS  4U 
#define  DMA_IFM_CH2BTDIFM_MSK  BIT(DMA_IFM_CH2BTDIFM_POS)

#define  DMA_IFM_CH1TABIFM_POS  3U 
#define  DMA_IFM_CH1TABIFM_MSK  BIT(DMA_IFM_CH1TABIFM_POS)

#define  DMA_IFM_CH1BTDIFM_POS  2U 
#define  DMA_IFM_CH1BTDIFM_MSK  BIT(DMA_IFM_CH1BTDIFM_POS)

#define  DMA_IFM_CH0TABIFM_POS  1U 
#define  DMA_IFM_CH0TABIFM_MSK  BIT(DMA_IFM_CH0TABIFM_POS)

#define  DMA_IFM_CH0BTDIFM_POS  0U 
#define  DMA_IFM_CH0BTDIFM_MSK  BIT(DMA_IFM_CH0BTDIFM_POS)

/****************** Bit definition for DMA_ICR register ************************/

#define  DMA_ICR_CH5TABICR_POS  11U 
#define  DMA_ICR_CH5TABICR_MSK  BIT(DMA_ICR_CH5TABICR_POS)

#define  DMA_ICR_CH5BTDICR_POS  10U 
#define  DMA_ICR_CH5BTDICR_MSK  BIT(DMA_ICR_CH5BTDICR_POS)

#define  DMA_ICR_CH4TABICR_POS  9U 
#define  DMA_ICR_CH4TABICR_MSK  BIT(DMA_ICR_CH4TABICR_POS)

#define  DMA_ICR_CH4BTDICR_POS  8U 
#define  DMA_ICR_CH4BTDICR_MSK  BIT(DMA_ICR_CH4BTDICR_POS)

#define  DMA_ICR_CH3TABICR_POS  7U 
#define  DMA_ICR_CH3TABICR_MSK  BIT(DMA_ICR_CH3TABICR_POS)

#define  DMA_ICR_CH3BTDICR_POS  6U 
#define  DMA_ICR_CH3BTDICR_MSK  BIT(DMA_ICR_CH3BTDICR_POS)

#define  DMA_ICR_CH2TABICR_POS  5U 
#define  DMA_ICR_CH2TABICR_MSK  BIT(DMA_ICR_CH2TABICR_POS)

#define  DMA_ICR_CH2BTDICR_POS  4U 
#define  DMA_ICR_CH2BTDICR_MSK  BIT(DMA_ICR_CH2BTDICR_POS)

#define  DMA_ICR_CH1TABICR_POS  3U 
#define  DMA_ICR_CH1TABICR_MSK  BIT(DMA_ICR_CH1TABICR_POS)

#define  DMA_ICR_CH1BTDICR_POS  2U 
#define  DMA_ICR_CH1BTDICR_MSK  BIT(DMA_ICR_CH1BTDICR_POS)

#define  DMA_ICR_CH0TABICR_POS  1U 
#define  DMA_ICR_CH0TABICR_MSK  BIT(DMA_ICR_CH0TABICR_POS)

#define  DMA_ICR_CH0BTDICR_POS  0U 
#define  DMA_ICR_CH0BTDICR_MSK  BIT(DMA_ICR_CH0BTDICR_POS)

/****************** Bit definition for DMA_EMSG register ************************/

#define  DMA_EMSG_CH5PFSER_POS  23U 
#define  DMA_EMSG_CH5PFSER_MSK  BIT(DMA_EMSG_CH5PFSER_POS)

#define  DMA_EMSG_CH5PFOV_POS  22U 
#define  DMA_EMSG_CH5PFOV_MSK  BIT(DMA_EMSG_CH5PFOV_POS)

#define  DMA_EMSG_CH5SETBUER_POS  21U 
#define  DMA_EMSG_CH5SETBUER_MSK  BIT(DMA_EMSG_CH5SETBUER_POS)

#define  DMA_EMSG_CH5SETBCER_POS  20U 
#define  DMA_EMSG_CH5SETBCER_MSK  BIT(DMA_EMSG_CH5SETBCER_POS)

#define  DMA_EMSG_CH4PFSER_POS  19U 
#define  DMA_EMSG_CH4PFSER_MSK  BIT(DMA_EMSG_CH4PFSER_POS)

#define  DMA_EMSG_CH4PFOV_POS  18U 
#define  DMA_EMSG_CH4PFOV_MSK  BIT(DMA_EMSG_CH4PFOV_POS)

#define  DMA_EMSG_CH4SETBUER_POS  17U 
#define  DMA_EMSG_CH4SETBUER_MSK  BIT(DMA_EMSG_CH4SETBUER_POS)

#define  DMA_EMSG_CH4SETBCER_POS  16U 
#define  DMA_EMSG_CH4SETBCER_MSK  BIT(DMA_EMSG_CH4SETBCER_POS)

#define  DMA_EMSG_CH3PFSER_POS  15U 
#define  DMA_EMSG_CH3PFSER_MSK  BIT(DMA_EMSG_CH3PFSER_POS)

#define  DMA_EMSG_CH3PFOV_POS  14U 
#define  DMA_EMSG_CH3PFOV_MSK  BIT(DMA_EMSG_CH3PFOV_POS)

#define  DMA_EMSG_CH3SETBUER_POS  13U 
#define  DMA_EMSG_CH3SETBUER_MSK  BIT(DMA_EMSG_CH3SETBUER_POS)

#define  DMA_EMSG_CH3SETBCER_POS  12U 
#define  DMA_EMSG_CH3SETBCER_MSK  BIT(DMA_EMSG_CH3SETBCER_POS)

#define  DMA_EMSG_CH2PFSER_POS  11U 
#define  DMA_EMSG_CH2PFSER_MSK  BIT(DMA_EMSG_CH2PFSER_POS)

#define  DMA_EMSG_CH2PFOV_POS  10U 
#define  DMA_EMSG_CH2PFOV_MSK  BIT(DMA_EMSG_CH2PFOV_POS)

#define  DMA_EMSG_CH2SETBUER_POS  9U 
#define  DMA_EMSG_CH2SETBUER_MSK  BIT(DMA_EMSG_CH2SETBUER_POS)

#define  DMA_EMSG_CH2SETBCER_POS  8U 
#define  DMA_EMSG_CH2SETBCER_MSK  BIT(DMA_EMSG_CH2SETBCER_POS)

#define  DMA_EMSG_CH1PFSER_POS  7U 
#define  DMA_EMSG_CH1PFSER_MSK  BIT(DMA_EMSG_CH1PFSER_POS)

#define  DMA_EMSG_CH1PFOV_POS  6U 
#define  DMA_EMSG_CH1PFOV_MSK  BIT(DMA_EMSG_CH1PFOV_POS)

#define  DMA_EMSG_CH1SETBUER_POS  5U 
#define  DMA_EMSG_CH1SETBUER_MSK  BIT(DMA_EMSG_CH1SETBUER_POS)

#define  DMA_EMSG_CH1SETBCER_POS  4U 
#define  DMA_EMSG_CH1SETBCER_MSK  BIT(DMA_EMSG_CH1SETBCER_POS)

#define  DMA_EMSG_CH0PFSER_POS  3U 
#define  DMA_EMSG_CH0PFSER_MSK  BIT(DMA_EMSG_CH0PFSER_POS)

#define  DMA_EMSG_CH0PFOV_POS  2U 
#define  DMA_EMSG_CH0PFOV_MSK  BIT(DMA_EMSG_CH0PFOV_POS)

#define  DMA_EMSG_CH0SETBUER_POS  1U 
#define  DMA_EMSG_CH0SETBUER_MSK  BIT(DMA_EMSG_CH0SETBUER_POS)

#define  DMA_EMSG_CH0SETBCER_POS  0U 
#define  DMA_EMSG_CH0SETBCER_MSK  BIT(DMA_EMSG_CH0SETBCER_POS)

/****************** Bit definition for DMA_CSR0 register ************************/

#define  DMA_CSR0_DINCOS_POS  30U 
#define  DMA_CSR0_DINCOS_MSK  BIT(DMA_CSR0_DINCOS_POS)

#define  DMA_CSR0_DBUSEL_POSS  27U 
#define  DMA_CSR0_DBUSEL_POSE  29U 
#define  DMA_CSR0_DBUSEL_MSK  BITS(DMA_CSR0_DBUSEL_POSS,DMA_CSR0_DBUSEL_POSE)

#define  DMA_CSR0_DDWSEL_POSS  25U 
#define  DMA_CSR0_DDWSEL_POSE  26U 
#define  DMA_CSR0_DDWSEL_MSK  BITS(DMA_CSR0_DDWSEL_POSS,DMA_CSR0_DDWSEL_POSE)

#define  DMA_CSR0_DINC_POS  24U 
#define  DMA_CSR0_DINC_MSK  BIT(DMA_CSR0_DINC_POS)

#define  DMA_CSR0_SINCOS_POS  22U 
#define  DMA_CSR0_SINCOS_MSK  BIT(DMA_CSR0_SINCOS_POS)

#define  DMA_CSR0_SBUSEL_POSS  19U 
#define  DMA_CSR0_SBUSEL_POSE  21U 
#define  DMA_CSR0_SBUSEL_MSK  BITS(DMA_CSR0_SBUSEL_POSS,DMA_CSR0_SBUSEL_POSE)

#define  DMA_CSR0_SDWSEL_POSS  17U 
#define  DMA_CSR0_SDWSEL_POSE  18U 
#define  DMA_CSR0_SDWSEL_MSK  BITS(DMA_CSR0_SDWSEL_POSS,DMA_CSR0_SDWSEL_POSE)

#define  DMA_CSR0_SINC_POS  16U 
#define  DMA_CSR0_SINC_MSK  BIT(DMA_CSR0_SINC_POS)

#define  DMA_CSR0_PHSS_POSS  9U 
#define  DMA_CSR0_PHSS_POSE  15U 
#define  DMA_CSR0_PHSS_MSK  BITS(DMA_CSR0_PHSS_POSS,DMA_CSR0_PHSS_POSE)

#define  DMA_CSR0_CHPRI_POSS  6U 
#define  DMA_CSR0_CHPRI_POSE  8U 
#define  DMA_CSR0_CHPRI_MSK  BITS(DMA_CSR0_CHPRI_POSS,DMA_CSR0_CHPRI_POSE)

#define  DMA_CSR0_MODESEL_POSS  4U 
#define  DMA_CSR0_MODESEL_POSE  5U 
#define  DMA_CSR0_MODESEL_MSK  BITS(DMA_CSR0_MODESEL_POSS,DMA_CSR0_MODESEL_POSE)

#define  DMA_CSR0_DIRMDEN_POS  3U 
#define  DMA_CSR0_DIRMDEN_MSK  BIT(DMA_CSR0_DIRMDEN_POS)

#define  DMA_CSR0_PFCTRL_POS  2U 
#define  DMA_CSR0_PFCTRL_MSK  BIT(DMA_CSR0_PFCTRL_POS)

#define  DMA_CSR0_CIRC_POS  1U 
#define  DMA_CSR0_CIRC_MSK  BIT(DMA_CSR0_CIRC_POS)

#define  DMA_CSR0_CHEN_POS  0U 
#define  DMA_CSR0_CHEN_MSK  BIT(DMA_CSR0_CHEN_POS)

/****************** Bit definition for DMA_SAR0 register ************************/

#define  DMA_SAR0_SAR_POSS  0U 
#define  DMA_SAR0_SAR_POSE  31U 
#define  DMA_SAR0_SAR_MSK  BITS(DMA_SAR0_SAR_POSS,DMA_SAR0_SAR_POSE)

/****************** Bit definition for DMA_DAR0 register ************************/

#define  DMA_DAR0_DAR_POSS  0U 
#define  DMA_DAR0_DAR_POSE  31U 
#define  DMA_DAR0_DAR_MSK  BITS(DMA_DAR0_DAR_POSS,DMA_DAR0_DAR_POSE)

/****************** Bit definition for DMA_BCR0 register ************************/

#define  DMA_BCR0_CBCR_POSS  16U 
#define  DMA_BCR0_CBCR_POSE  31U 
#define  DMA_BCR0_CBCR_MSK  BITS(DMA_BCR0_CBCR_POSS,DMA_BCR0_CBCR_POSE)

#define  DMA_BCR0_BCR_POSS  0U 
#define  DMA_BCR0_BCR_POSE  15U 
#define  DMA_BCR0_BCR_MSK  BITS(DMA_BCR0_BCR_POSS,DMA_BCR0_BCR_POSE)

/****************** Bit definition for DMA_CSR1 register ************************/

#define  DMA_CSR1_DINCOS_POS  30U 
#define  DMA_CSR1_DINCOS_MSK  BIT(DMA_CSR1_DINCOS_POS)

#define  DMA_CSR1_DBUSEL_POSS  27U 
#define  DMA_CSR1_DBUSEL_POSE  29U 
#define  DMA_CSR1_DBUSEL_MSK  BITS(DMA_CSR1_DBUSEL_POSS,DMA_CSR1_DBUSEL_POSE)

#define  DMA_CSR1_DDWSEL_POSS  25U 
#define  DMA_CSR1_DDWSEL_POSE  26U 
#define  DMA_CSR1_DDWSEL_MSK  BITS(DMA_CSR1_DDWSEL_POSS,DMA_CSR1_DDWSEL_POSE)

#define  DMA_CSR1_DINC_POS  24U 
#define  DMA_CSR1_DINC_MSK  BIT(DMA_CSR1_DINC_POS)

#define  DMA_CSR1_SINCOS_POS  22U 
#define  DMA_CSR1_SINCOS_MSK  BIT(DMA_CSR1_SINCOS_POS)

#define  DMA_CSR1_SBUSEL_POSS  19U 
#define  DMA_CSR1_SBUSEL_POSE  21U 
#define  DMA_CSR1_SBUSEL_MSK  BITS(DMA_CSR1_SBUSEL_POSS,DMA_CSR1_SBUSEL_POSE)

#define  DMA_CSR1_SDWSEL_POSS  17U 
#define  DMA_CSR1_SDWSEL_POSE  18U 
#define  DMA_CSR1_SDWSEL_MSK  BITS(DMA_CSR1_SDWSEL_POSS,DMA_CSR1_SDWSEL_POSE)

#define  DMA_CSR1_SINC_POS  16U 
#define  DMA_CSR1_SINC_MSK  BIT(DMA_CSR1_SINC_POS)

#define  DMA_CSR1_PHSS_POSS  9U 
#define  DMA_CSR1_PHSS_POSE  15U 
#define  DMA_CSR1_PHSS_MSK  BITS(DMA_CSR1_PHSS_POSS,DMA_CSR1_PHSS_POSE)

#define  DMA_CSR1_CHPRI_POSS  6U 
#define  DMA_CSR1_CHPRI_POSE  8U 
#define  DMA_CSR1_CHPRI_MSK  BITS(DMA_CSR1_CHPRI_POSS,DMA_CSR1_CHPRI_POSE)

#define  DMA_CSR1_MODESEL_POSS  4U 
#define  DMA_CSR1_MODESEL_POSE  5U 
#define  DMA_CSR1_MODESEL_MSK  BITS(DMA_CSR1_MODESEL_POSS,DMA_CSR1_MODESEL_POSE)

#define  DMA_CSR1_DIRMDEN_POS  3U 
#define  DMA_CSR1_DIRMDEN_MSK  BIT(DMA_CSR1_DIRMDEN_POS)

#define  DMA_CSR1_PFCTRL_POS  2U 
#define  DMA_CSR1_PFCTRL_MSK  BIT(DMA_CSR1_PFCTRL_POS)

#define  DMA_CSR1_CIRC_POS  1U 
#define  DMA_CSR1_CIRC_MSK  BIT(DMA_CSR1_CIRC_POS)

#define  DMA_CSR1_CHEN_POS  0U 
#define  DMA_CSR1_CHEN_MSK  BIT(DMA_CSR1_CHEN_POS)

/****************** Bit definition for DMA_SAR1 register ************************/

#define  DMA_SAR1_SAR_POSS  0U 
#define  DMA_SAR1_SAR_POSE  31U 
#define  DMA_SAR1_SAR_MSK  BITS(DMA_SAR1_SAR_POSS,DMA_SAR1_SAR_POSE)

/****************** Bit definition for DMA_DAR1 register ************************/

#define  DMA_DAR1_DAR_POSS  0U 
#define  DMA_DAR1_DAR_POSE  31U 
#define  DMA_DAR1_DAR_MSK  BITS(DMA_DAR1_DAR_POSS,DMA_DAR1_DAR_POSE)

/****************** Bit definition for DMA_BCR1 register ************************/

#define  DMA_BCR1_CBCR_POSS  16U 
#define  DMA_BCR1_CBCR_POSE  31U 
#define  DMA_BCR1_CBCR_MSK  BITS(DMA_BCR1_CBCR_POSS,DMA_BCR1_CBCR_POSE)

#define  DMA_BCR1_BCR_POSS  0U 
#define  DMA_BCR1_BCR_POSE  15U 
#define  DMA_BCR1_BCR_MSK  BITS(DMA_BCR1_BCR_POSS,DMA_BCR1_BCR_POSE)

/****************** Bit definition for DMA_CSR2 register ************************/

#define  DMA_CSR2_DINCOS_POS  30U 
#define  DMA_CSR2_DINCOS_MSK  BIT(DMA_CSR2_DINCOS_POS)

#define  DMA_CSR2_DBUSEL_POSS  27U 
#define  DMA_CSR2_DBUSEL_POSE  29U 
#define  DMA_CSR2_DBUSEL_MSK  BITS(DMA_CSR2_DBUSEL_POSS,DMA_CSR2_DBUSEL_POSE)

#define  DMA_CSR2_DDWSEL_POSS  25U 
#define  DMA_CSR2_DDWSEL_POSE  26U 
#define  DMA_CSR2_DDWSEL_MSK  BITS(DMA_CSR2_DDWSEL_POSS,DMA_CSR2_DDWSEL_POSE)

#define  DMA_CSR2_DINC_POS  24U 
#define  DMA_CSR2_DINC_MSK  BIT(DMA_CSR2_DINC_POS)

#define  DMA_CSR2_SINCOS_POS  22U 
#define  DMA_CSR2_SINCOS_MSK  BIT(DMA_CSR2_SINCOS_POS)

#define  DMA_CSR2_SBUSEL_POSS  19U 
#define  DMA_CSR2_SBUSEL_POSE  21U 
#define  DMA_CSR2_SBUSEL_MSK  BITS(DMA_CSR2_SBUSEL_POSS,DMA_CSR2_SBUSEL_POSE)

#define  DMA_CSR2_SDWSEL_POSS  17U 
#define  DMA_CSR2_SDWSEL_POSE  18U 
#define  DMA_CSR2_SDWSEL_MSK  BITS(DMA_CSR2_SDWSEL_POSS,DMA_CSR2_SDWSEL_POSE)

#define  DMA_CSR2_SINC_POS  16U 
#define  DMA_CSR2_SINC_MSK  BIT(DMA_CSR2_SINC_POS)

#define  DMA_CSR2_PHSS_POSS  9U 
#define  DMA_CSR2_PHSS_POSE  15U 
#define  DMA_CSR2_PHSS_MSK  BITS(DMA_CSR2_PHSS_POSS,DMA_CSR2_PHSS_POSE)

#define  DMA_CSR2_CHPRI_POSS  6U 
#define  DMA_CSR2_CHPRI_POSE  8U 
#define  DMA_CSR2_CHPRI_MSK  BITS(DMA_CSR2_CHPRI_POSS,DMA_CSR2_CHPRI_POSE)

#define  DMA_CSR2_MODESEL_POSS  4U 
#define  DMA_CSR2_MODESEL_POSE  5U 
#define  DMA_CSR2_MODESEL_MSK  BITS(DMA_CSR2_MODESEL_POSS,DMA_CSR2_MODESEL_POSE)

#define  DMA_CSR2_DIRMDEN_POS  3U 
#define  DMA_CSR2_DIRMDEN_MSK  BIT(DMA_CSR2_DIRMDEN_POS)

#define  DMA_CSR2_PFCTRL_POS  2U 
#define  DMA_CSR2_PFCTRL_MSK  BIT(DMA_CSR2_PFCTRL_POS)

#define  DMA_CSR2_CIRC_POS  1U 
#define  DMA_CSR2_CIRC_MSK  BIT(DMA_CSR2_CIRC_POS)

#define  DMA_CSR2_CHEN_POS  0U 
#define  DMA_CSR2_CHEN_MSK  BIT(DMA_CSR2_CHEN_POS)

/****************** Bit definition for DMA_SAR2 register ************************/

#define  DMA_SAR2_SAR_POSS  0U 
#define  DMA_SAR2_SAR_POSE  31U 
#define  DMA_SAR2_SAR_MSK  BITS(DMA_SAR2_SAR_POSS,DMA_SAR2_SAR_POSE)

/****************** Bit definition for DMA_DAR2 register ************************/

#define  DMA_DAR2_DAR_POSS  0U 
#define  DMA_DAR2_DAR_POSE  31U 
#define  DMA_DAR2_DAR_MSK  BITS(DMA_DAR2_DAR_POSS,DMA_DAR2_DAR_POSE)

/****************** Bit definition for DMA_BCR2 register ************************/

#define  DMA_BCR2_CBCR_POSS  16U 
#define  DMA_BCR2_CBCR_POSE  31U 
#define  DMA_BCR2_CBCR_MSK  BITS(DMA_BCR2_CBCR_POSS,DMA_BCR2_CBCR_POSE)

#define  DMA_BCR2_BCR_POSS  0U 
#define  DMA_BCR2_BCR_POSE  15U 
#define  DMA_BCR2_BCR_MSK  BITS(DMA_BCR2_BCR_POSS,DMA_BCR2_BCR_POSE)

/****************** Bit definition for DMA_CSR3 register ************************/

#define  DMA_CSR3_DINCOS_POS  30U 
#define  DMA_CSR3_DINCOS_MSK  BIT(DMA_CSR3_DINCOS_POS)

#define  DMA_CSR3_DBUSEL_POSS  27U 
#define  DMA_CSR3_DBUSEL_POSE  29U 
#define  DMA_CSR3_DBUSEL_MSK  BITS(DMA_CSR3_DBUSEL_POSS,DMA_CSR3_DBUSEL_POSE)

#define  DMA_CSR3_DDWSEL_POSS  25U 
#define  DMA_CSR3_DDWSEL_POSE  26U 
#define  DMA_CSR3_DDWSEL_MSK  BITS(DMA_CSR3_DDWSEL_POSS,DMA_CSR3_DDWSEL_POSE)

#define  DMA_CSR3_DINC_POS  24U 
#define  DMA_CSR3_DINC_MSK  BIT(DMA_CSR3_DINC_POS)

#define  DMA_CSR3_SINCOS_POS  22U 
#define  DMA_CSR3_SINCOS_MSK  BIT(DMA_CSR3_SINCOS_POS)

#define  DMA_CSR3_SBUSEL_POSS  19U 
#define  DMA_CSR3_SBUSEL_POSE  21U 
#define  DMA_CSR3_SBUSEL_MSK  BITS(DMA_CSR3_SBUSEL_POSS,DMA_CSR3_SBUSEL_POSE)

#define  DMA_CSR3_SDWSEL_POSS  17U 
#define  DMA_CSR3_SDWSEL_POSE  18U 
#define  DMA_CSR3_SDWSEL_MSK  BITS(DMA_CSR3_SDWSEL_POSS,DMA_CSR3_SDWSEL_POSE)

#define  DMA_CSR3_SINC_POS  16U 
#define  DMA_CSR3_SINC_MSK  BIT(DMA_CSR3_SINC_POS)

#define  DMA_CSR3_PHSS_POSS  9U 
#define  DMA_CSR3_PHSS_POSE  15U 
#define  DMA_CSR3_PHSS_MSK  BITS(DMA_CSR3_PHSS_POSS,DMA_CSR3_PHSS_POSE)

#define  DMA_CSR3_CHPRI_POSS  6U 
#define  DMA_CSR3_CHPRI_POSE  8U 
#define  DMA_CSR3_CHPRI_MSK  BITS(DMA_CSR3_CHPRI_POSS,DMA_CSR3_CHPRI_POSE)

#define  DMA_CSR3_MODESEL_POSS  4U 
#define  DMA_CSR3_MODESEL_POSE  5U 
#define  DMA_CSR3_MODESEL_MSK  BITS(DMA_CSR3_MODESEL_POSS,DMA_CSR3_MODESEL_POSE)

#define  DMA_CSR3_DIRMDEN_POS  3U 
#define  DMA_CSR3_DIRMDEN_MSK  BIT(DMA_CSR3_DIRMDEN_POS)

#define  DMA_CSR3_PFCTRL_POS  2U 
#define  DMA_CSR3_PFCTRL_MSK  BIT(DMA_CSR3_PFCTRL_POS)

#define  DMA_CSR3_CIRC_POS  1U 
#define  DMA_CSR3_CIRC_MSK  BIT(DMA_CSR3_CIRC_POS)

#define  DMA_CSR3_CHEN_POS  0U 
#define  DMA_CSR3_CHEN_MSK  BIT(DMA_CSR3_CHEN_POS)

/****************** Bit definition for DMA_SAR3 register ************************/

#define  DMA_SAR3_SAR_POSS  0U 
#define  DMA_SAR3_SAR_POSE  31U 
#define  DMA_SAR3_SAR_MSK  BITS(DMA_SAR3_SAR_POSS,DMA_SAR3_SAR_POSE)

/****************** Bit definition for DMA_DAR3 register ************************/

#define  DMA_DAR3_DAR_POSS  0U 
#define  DMA_DAR3_DAR_POSE  31U 
#define  DMA_DAR3_DAR_MSK  BITS(DMA_DAR3_DAR_POSS,DMA_DAR3_DAR_POSE)

/****************** Bit definition for DMA_BCR3 register ************************/

#define  DMA_BCR3_CBCR_POSS  16U 
#define  DMA_BCR3_CBCR_POSE  31U 
#define  DMA_BCR3_CBCR_MSK  BITS(DMA_BCR3_CBCR_POSS,DMA_BCR3_CBCR_POSE)

#define  DMA_BCR3_BCR_POSS  0U 
#define  DMA_BCR3_BCR_POSE  15U 
#define  DMA_BCR3_BCR_MSK  BITS(DMA_BCR3_BCR_POSS,DMA_BCR3_BCR_POSE)

/****************** Bit definition for DMA_CSR4 register ************************/

#define  DMA_CSR4_DINCOS_POS  30U 
#define  DMA_CSR4_DINCOS_MSK  BIT(DMA_CSR4_DINCOS_POS)

#define  DMA_CSR4_DBUSEL_POSS  27U 
#define  DMA_CSR4_DBUSEL_POSE  29U 
#define  DMA_CSR4_DBUSEL_MSK  BITS(DMA_CSR4_DBUSEL_POSS,DMA_CSR4_DBUSEL_POSE)

#define  DMA_CSR4_DDWSEL_POSS  25U 
#define  DMA_CSR4_DDWSEL_POSE  26U 
#define  DMA_CSR4_DDWSEL_MSK  BITS(DMA_CSR4_DDWSEL_POSS,DMA_CSR4_DDWSEL_POSE)

#define  DMA_CSR4_DINC_POS  24U 
#define  DMA_CSR4_DINC_MSK  BIT(DMA_CSR4_DINC_POS)

#define  DMA_CSR4_SINCOS_POS  22U 
#define  DMA_CSR4_SINCOS_MSK  BIT(DMA_CSR4_SINCOS_POS)

#define  DMA_CSR4_SBUSEL_POSS  19U 
#define  DMA_CSR4_SBUSEL_POSE  21U 
#define  DMA_CSR4_SBUSEL_MSK  BITS(DMA_CSR4_SBUSEL_POSS,DMA_CSR4_SBUSEL_POSE)

#define  DMA_CSR4_SDWSEL_POSS  17U 
#define  DMA_CSR4_SDWSEL_POSE  18U 
#define  DMA_CSR4_SDWSEL_MSK  BITS(DMA_CSR4_SDWSEL_POSS,DMA_CSR4_SDWSEL_POSE)

#define  DMA_CSR4_SINC_POS  16U 
#define  DMA_CSR4_SINC_MSK  BIT(DMA_CSR4_SINC_POS)

#define  DMA_CSR4_PHSS_POSS  9U 
#define  DMA_CSR4_PHSS_POSE  15U 
#define  DMA_CSR4_PHSS_MSK  BITS(DMA_CSR4_PHSS_POSS,DMA_CSR4_PHSS_POSE)

#define  DMA_CSR4_CHPRI_POSS  6U 
#define  DMA_CSR4_CHPRI_POSE  8U 
#define  DMA_CSR4_CHPRI_MSK  BITS(DMA_CSR4_CHPRI_POSS,DMA_CSR4_CHPRI_POSE)

#define  DMA_CSR4_MODESEL_POSS  4U 
#define  DMA_CSR4_MODESEL_POSE  5U 
#define  DMA_CSR4_MODESEL_MSK  BITS(DMA_CSR4_MODESEL_POSS,DMA_CSR4_MODESEL_POSE)

#define  DMA_CSR4_DIRMDEN_POS  3U 
#define  DMA_CSR4_DIRMDEN_MSK  BIT(DMA_CSR4_DIRMDEN_POS)

#define  DMA_CSR4_PFCTRL_POS  2U 
#define  DMA_CSR4_PFCTRL_MSK  BIT(DMA_CSR4_PFCTRL_POS)

#define  DMA_CSR4_CIRC_POS  1U 
#define  DMA_CSR4_CIRC_MSK  BIT(DMA_CSR4_CIRC_POS)

#define  DMA_CSR4_CHEN_POS  0U 
#define  DMA_CSR4_CHEN_MSK  BIT(DMA_CSR4_CHEN_POS)

/****************** Bit definition for DMA_SAR4 register ************************/

#define  DMA_SAR4_SAR_POSS  0U 
#define  DMA_SAR4_SAR_POSE  31U 
#define  DMA_SAR4_SAR_MSK  BITS(DMA_SAR4_SAR_POSS,DMA_SAR4_SAR_POSE)

/****************** Bit definition for DMA_DAR4 register ************************/

#define  DMA_DAR4_DAR_POSS  0U 
#define  DMA_DAR4_DAR_POSE  31U 
#define  DMA_DAR4_DAR_MSK  BITS(DMA_DAR4_DAR_POSS,DMA_DAR4_DAR_POSE)

/****************** Bit definition for DMA_BCR4 register ************************/

#define  DMA_BCR4_CBCR_POSS  16U 
#define  DMA_BCR4_CBCR_POSE  31U 
#define  DMA_BCR4_CBCR_MSK  BITS(DMA_BCR4_CBCR_POSS,DMA_BCR4_CBCR_POSE)

#define  DMA_BCR4_BCR_POSS  0U 
#define  DMA_BCR4_BCR_POSE  15U 
#define  DMA_BCR4_BCR_MSK  BITS(DMA_BCR4_BCR_POSS,DMA_BCR4_BCR_POSE)

/****************** Bit definition for DMA_CSR5 register ************************/

#define  DMA_CSR5_DINCOS_POS  30U 
#define  DMA_CSR5_DINCOS_MSK  BIT(DMA_CSR5_DINCOS_POS)

#define  DMA_CSR5_DBUSEL_POSS  27U 
#define  DMA_CSR5_DBUSEL_POSE  29U 
#define  DMA_CSR5_DBUSEL_MSK  BITS(DMA_CSR5_DBUSEL_POSS,DMA_CSR5_DBUSEL_POSE)

#define  DMA_CSR5_DDWSEL_POSS  25U 
#define  DMA_CSR5_DDWSEL_POSE  26U 
#define  DMA_CSR5_DDWSEL_MSK  BITS(DMA_CSR5_DDWSEL_POSS,DMA_CSR5_DDWSEL_POSE)

#define  DMA_CSR5_DINC_POS  24U 
#define  DMA_CSR5_DINC_MSK  BIT(DMA_CSR5_DINC_POS)

#define  DMA_CSR5_SINCOS_POS  22U 
#define  DMA_CSR5_SINCOS_MSK  BIT(DMA_CSR5_SINCOS_POS)

#define  DMA_CSR5_SBUSEL_POSS  19U 
#define  DMA_CSR5_SBUSEL_POSE  21U 
#define  DMA_CSR5_SBUSEL_MSK  BITS(DMA_CSR5_SBUSEL_POSS,DMA_CSR5_SBUSEL_POSE)

#define  DMA_CSR5_SDWSEL_POSS  17U 
#define  DMA_CSR5_SDWSEL_POSE  18U 
#define  DMA_CSR5_SDWSEL_MSK  BITS(DMA_CSR5_SDWSEL_POSS,DMA_CSR5_SDWSEL_POSE)

#define  DMA_CSR5_SINC_POS  16U 
#define  DMA_CSR5_SINC_MSK  BIT(DMA_CSR5_SINC_POS)

#define  DMA_CSR5_PHSS_POSS  9U 
#define  DMA_CSR5_PHSS_POSE  15U 
#define  DMA_CSR5_PHSS_MSK  BITS(DMA_CSR5_PHSS_POSS,DMA_CSR5_PHSS_POSE)

#define  DMA_CSR5_CHPRI_POSS  6U 
#define  DMA_CSR5_CHPRI_POSE  8U 
#define  DMA_CSR5_CHPRI_MSK  BITS(DMA_CSR5_CHPRI_POSS,DMA_CSR5_CHPRI_POSE)

#define  DMA_CSR5_MODESEL_POSS  4U 
#define  DMA_CSR5_MODESEL_POSE  5U 
#define  DMA_CSR5_MODESEL_MSK  BITS(DMA_CSR5_MODESEL_POSS,DMA_CSR5_MODESEL_POSE)

#define  DMA_CSR5_DIRMDEN_POS  3U 
#define  DMA_CSR5_DIRMDEN_MSK  BIT(DMA_CSR5_DIRMDEN_POS)

#define  DMA_CSR5_PFCTRL_POS  2U 
#define  DMA_CSR5_PFCTRL_MSK  BIT(DMA_CSR5_PFCTRL_POS)

#define  DMA_CSR5_CIRC_POS  1U 
#define  DMA_CSR5_CIRC_MSK  BIT(DMA_CSR5_CIRC_POS)

#define  DMA_CSR5_CHEN_POS  0U 
#define  DMA_CSR5_CHEN_MSK  BIT(DMA_CSR5_CHEN_POS)

/****************** Bit definition for DMA_SAR5 register ************************/

#define  DMA_SAR5_SAR_POSS  0U 
#define  DMA_SAR5_SAR_POSE  31U 
#define  DMA_SAR5_SAR_MSK  BITS(DMA_SAR5_SAR_POSS,DMA_SAR5_SAR_POSE)

/****************** Bit definition for DMA_DAR5 register ************************/

#define  DMA_DAR5_DAR_POSS  0U 
#define  DMA_DAR5_DAR_POSE  31U 
#define  DMA_DAR5_DAR_MSK  BITS(DMA_DAR5_DAR_POSS,DMA_DAR5_DAR_POSE)

/****************** Bit definition for DMA_BCR5 register ************************/

#define  DMA_BCR5_CBCR_POSS  16U 
#define  DMA_BCR5_CBCR_POSE  31U 
#define  DMA_BCR5_CBCR_MSK  BITS(DMA_BCR5_CBCR_POSS,DMA_BCR5_CBCR_POSE)

#define  DMA_BCR5_BCR_POSS  0U 
#define  DMA_BCR5_BCR_POSE  15U 
#define  DMA_BCR5_BCR_MSK  BITS(DMA_BCR5_BCR_POSS,DMA_BCR5_BCR_POSE)

typedef struct
{
  __O uint32_t IER;
  __O uint32_t IDR;
  __I uint32_t IVS;
  __I uint32_t RIF;
  __I uint32_t IFM;
  __O uint32_t ICR;
  __I uint32_t EMSG;
  uint32_t RESERVED0 ;
  __IO uint32_t CSR0;
  __IO uint32_t SAR0;
  __IO uint32_t DAR0;
  __IO uint32_t BCR0;
  __IO uint32_t CSR1;
  __IO uint32_t SAR1;
  __IO uint32_t DAR1;
  __IO uint32_t BCR1;
  __IO uint32_t CSR2;
  __IO uint32_t SAR2;
  __IO uint32_t DAR2;
  __IO uint32_t BCR2;
  __IO uint32_t CSR3;
  __IO uint32_t SAR3;
  __IO uint32_t DAR3;
  __IO uint32_t BCR3;
  __IO uint32_t CSR4;
  __IO uint32_t SAR4;
  __IO uint32_t DAR4;
  __IO uint32_t BCR4;
  __IO uint32_t CSR5;
  __IO uint32_t SAR5;
  __IO uint32_t DAR5;
  __IO uint32_t BCR5;
} DMA_TypeDef;





#endif
